1. Field of the Invention
The invention relates to a unit containing a plurality of direct-access random access memory cells, and comprising, inter alia, a unit selection input and a parellel multi-bit input for the address data presented to the unit, equipped with buffer circuits which, for each input bit, possess a pair of output connections on which, in read or write mode, two signals which are complementary to one another are present.
2. Description of the Related Art
It is known form the U.S. Pat. No. 4,412,309 (Kuo) to provide an electrically erasable programmable read only memory (EEPROM) with circuit means in order that two normally complementary signals for an address bit exhibit the same significant state, when a deselection signal is present at the unit selection input. When the two said signals exhibit the same significant state, several rows or columns can be programmed simultaneously. As a result the amount of programming time is reduced. Such a reduction is necessary because otherwise a comparatively large amount of time (measured in seconds) is necessary for programming an EEPROM in relation to the time which is necessary for reading the contents of an EEPROM.